(Nasdaq: SNPS) is a leading provider of electronic design automation (EDA) software tools for integrated circuit design worldwide. To provide advanced IC design and validation platform for the global electronics market, dedicated to the development of complex system on chip (SoC). Synopsys also provides intellectual property and design services that simplify the design process and speed products to market.
The company size
Synopsys is headquartered in Mountain View, California, and has more than 60 offices in North America, Europe, and Asia.
Since entering the Chinese market in 1995, Synopsys has been committed to accelerating the development of the IC design industry in China. Our team and business in China have maintained healthy growth. Over the past four years, Synopsys' sales in China have grown by an average of 70%.
The 2002 acquisition of Avant! Since then, Synopsys has become a leading EDA tool provider of complete IC design solutions for both front and back ends. This is also the first time in EDA history that a single EDA company has integrated the industry's best front-end and back-end design tools. In China, Synopsys has established two r&d centers in Shanghai and Beijing, integrating more than 200 r&d staff. Synopsys China developers work with us headquarters to develop new design tools for IC design engineers around the world and continue to provide in-depth support to China's IC design industry. This is Synopsys' largest IC design tools facility outside the United States. Therefore, China has become one of the global IC design tools research and development centers.
By working with a strategic partner in China, Synopsys has moved beyond being an upstream tool supplier to become an active facilitator of the industry chain. Through cooperation with the "863" program of the Ministry of Science and Technology, Synopsys provides a standardized advanced IC design environment for seven national IC industrialization bases; Through cooperation with the Chinese Academy of Sciences and leading universities, support research and talent training in China to develop IC design methods based on processes of 0.13 micron and below; Through the joint project "COMIP" with Datang Group, promote the industrialization of tD-SCDMA technology, which is the third generation of mobile communication with independent intellectual property rights in China; By cooperating with SMIC and other local IC Foundry to develop the reference design process, it is convenient for local design companies to produce wafers.
At the same time, Synopsys is committed to hiring and training local talents, establishing a professional and high-quality marketing and sales team, regulating the sales behavior in the domestic EDA market, establishing the best technical support team in China, establishing the Chinese customer after-sales service support center and the first 800 technical support hotline in the domestic EDA industry. For Chinese users and other users in the world to provide synchronization or even better technical service support.
Synopsys is committed to developing together with China's IC industry. Regardless of the turbulent changes in China's IC design industry in the past few years, it has never shaken the determination of common development. Synopsys is the only EDA company that has consistently provided direct technical promotion consulting, services and support to Chinese users over the past eight years. In China, there are four representative offices in Beijing, Shanghai, Hong Kong and Shenzhen, which are responsible for market development, sales, technical support, etc., with a total of 50 people. And has two r&d centers in Shanghai and Beijing, more than 200 EDA tool r&d personnel.
Synopsys' main business in China has also shifted from promoting EDA tools to providing customized solutions based on consultation and value creation.
Synopsys China has also grown from an EDA sales branch to a high-tech company with business consulting, technical support and IC design tool development rooted in China's IC industry.
The main products
Astro is Synopsys design environment for design optimization, layout, and wiring for ultra-deep submicron IC designs. Astro can meet the engineering and technical requirements of 50 million gate, clock frequency GHz, SoC designs produced in 0.10 and below process lines. Astro's high performance optimization and layout capabilities are largely due to the two latest technologies Synopsys has integrated into it: The PhySiSys and Milkyway DUO architectures.
DFT Compiler provides original "test synthesis once" techniques and solutions. It integrates with the Design Compiler and Physical Compiler family of products and includes powerful scanning and testability Design analysis, synthesis, and validation techniques. DFT Compiler enables designers to quickly and conveniently realize high-quality test analysis at the early stage of the design process, ensuring that both timing requirements and test coverage requirements are met at the same time. DFT Compiler also supports the checking of scan test design rules at RTL level and gate level, the insertion and optimization of scan chain given constraints, and the analysis of failure coverage.
TetraMAX ATPG is the industry's most powerful and easy-to-use automated test vector generation tool. For different designs, TetraMAX can generate the smallest set of test vectors with the highest fault coverage in the shortest time. TetraMAX supports full and incomplete scan designs, as well as fault simulation and analysis capabilities.
The Vera verification system addresses the need for verification, allowing efficient, intelligent, high-level functional verification. Vera verification systems have been widely used by Sun, NEC, Cisco and others to verify their actual products, from single ASIcs to computers and network systems composed of multiple ASIcs, from custom and semi-custom circuits to highly complex microprocessors. The basic idea of the Vera verification system is to generate flexible and self-checking test vectors, which are then combined into test-bench to test the designed circuit as fully as possible. Vera is designed for all levels of functional verification and features tight integration with the design environment, heuristic and fully random testing, data and protocol modeling, and functional code coverage analysis.
VCS is a compiled Verilog simulator that fully supports Verilog HDL, PLI, and SDF of OVI standards. The VCS has the highest simulation performance in the industry, with excellent memory management capability capable of supporting ten million gate ASIC designs, and its simulation accuracy fully meets the requirements of deep submicron ASIC Sign-off. A combination of metric-driven and event-driven algorithms, VCS is characterized by high performance, large scale and high precision, and is suitable for various stages from behavior level, RTL to sign-off. VCS has integrated all coverage testing features in CoverMeter and provides intelligent verification methods such as VeraLite and CycleC. VCS and Scirocco also support mixed-language emulation. Both VCS and Scirocco integrate the Virsim graphical user interface, which provides interaction and post-processing analysis of simulation results.
Power Compiler provides simple Power optimization ability, which can automatically minimize the Power consumption of the design and provide Power estimation before synthesis, so that designers can better plan Power distribution and complete low-power design in a short time. Embedded in Design Compiler/Physical Compiler, Power Compiler is the only comprehensive tool in the industry that can simultaneously optimize timing, Power consumption, and area.
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