Manufacturing:
TAPEOUT (TO) - Refers to submitting the final GDSII files to the foundry for processing.
FULL MASK - All masks in the manufacturing process are dedicated to a specific design.
MPW (Multi Project Wafer) - Multiple projects share a single wafer, allowing for several IC designs to be manufactured simultaneously. MPW involves sharing a mask set with other companies, while FULL MASK entails dedicated mask sets. If there's higher chip risk, starting with MPW allows testing before committing to FULL MASK production.
Foundry - Manufacturers specialized in chip fabrication, such as Taiwan Semiconductor Manufacturing Company (TSMC), Semiconductor Manufacturing International Corporation (SMIC), and United Microelectronics Corporation (UMC). Correspondingly, there are fabless companies, which are design firms without their own fabrication facilities.
Wafer - Silicon wafer used in semiconductor manufacturing.
Die - After being cut from the wafer, a single chip that requires encapsulation to become functional.
Chip - The final product of a semiconductor after it has been encapsulated.
Bump - Refers to the formation of raised points (made of materials like gold, tin-lead, lead-free, etc.) on the surface of a wafer, commonly used in flip-chip packaging.
Mask - A non-transparent template that is used to cover selected areas on a silicon wafer, allowing subsequent etching or diffusion processes to only affect the uncovered regions.
Chamber - A sealed space with a specific purpose, such as vacuum extraction, gas reactions, or metal deposition.
Dicing Wafer - The process of cutting a wafer into individual chips.
CVD (Chemical Vapor Deposition) - An advanced technology widely used in the field of materials preparation, which converts chemical substances from gases or gas mixtures into solid materials under high temperature and low-pressure environments.
PVD (Physical Vapor Deposition) - A method of depositing another material onto a substrate surface using ion plasma technology. It is a collective term for techniques such as sputtering and evaporation.
CMP (Chemical-Mechanical Polishing) - A process that utilizes a polishing pad covered with abrasive particles, along with chemical reagents, to achieve surface planarization of uneven crystal surfaces through a combination of chemical reactions and mechanical grinding actions.
CDA (Clean Dry Air) - Typically refers to air compressed between 60 and 110 psi, treated for purification and drying. It serves as the gas source for pneumatic components.
Diffusion - Commonly used in the semiconductor industry to introduce impurities into silicon wafers either through predeposition or ion implantation, by heating in a furnace tube to accomplish diffusion within several hours.
DI Water (Deionized Water) - Water that has been purified by killing bacteria, filtering, and removing impurities such as metal ions and particles from tap water or groundwater. It is specifically used in IC manufacturing.
Dopant - The process of introducing other atoms or ions into the original semiconductor material, either by implantation or diffusion, to alter its electrical properties.
Dummy Wafer - Silicon wafers used in the manufacturing process for certain auxiliary purposes, distinct from actual product wafers. Generally, they have lower quality requirements.
Fabless: It is a combination of "Fabrication" and "less" and refers to a business model in integrated circuit design where companies focus solely on design without owning a chip fabrication facility.
RTL (Register-Transfer Level): It is a hardware description language used to describe synchronous digital circuits.
SDC (Synopsys Design Constraints): It provides the design constraints file, which synthesis tools require to convert RTL into netlist. The SDC mainly describes the chip operating frequency, chip IO timing, design rules, special paths, and paths that do not require checking.
Verification: It refers to the methodology for chip functional verification, ensuring that the RTL matches the reference model.
Simulation: Simulation typically involves generating waveforms and is used for functional validation, verification, and power analysis of chips. It provides a visual representation of real-life scenarios.
IP (Intellectual Property): Design assets or completed functional circuit modules (cores, units) that are protected by intellectual property rights.
Design Rule: Due to the complex and delicate nature of semiconductor process technology, which can be influenced by different manufacturing equipment and process methods (RECIPE), it is necessary to have a set of specifications, known as "Design Rule," to define the technical requirements for successful manufacturing. These specifications are developed based on the needs, specifications, manufacturing equipment and process methods, process capabilities, and various electrical parameter specifications of different products.
Testing
CP (Chip Probing): Directly testing the wafer, where each individual Die in the entire wafer is tested to ensure that it meets the device characteristics or design specifications. This typically involves verifying voltage, current, timing, and functionality. It can be used to assess the manufacturing process level of the fab.
FT (Final Test): It's the last checkpoint before the chip leaves the factory. The testing targets the packaged chip, which undergoes packaging after CP testing. FT testing is conducted after packaging. It can be used to assess the packaging factory's manufacturing process level.
CP targets the wafer. If a Die is defective, there is no need to proceed with packaging, saving packaging and substrate costs.
After CP testing is completed, chip failures may still occur during the packaging process. Therefore, FT is necessary to remove defective chips.
Yield: The yield of a chip is closely related to the manufacturing process. Chips have a certain probability of failure, with larger chips having a higher failure rate.
IP (Intellectual Property): In integrated circuit design, IP refers to complete functional modules of integrated circuits that have been verified, are reusable, and have specific functions. IP can be classified by charging method into License and Loyalty.
License: Grants permission to use the IP, authorizing access to the IP.
Loyalty: Royalties paid by users for each chip after using the IP.
IP is the core component of chip design. Examples include USB, PCIe, CPU, etc., all of which are IPs integrated into the chip. The complexity of chips relies on IP reuse. For instance, chips with tens of millions or hundreds of millions of gates are achievable through IP reuse.
DUV: Deep Ultraviolet Rays
EUV: Extreme Ultraviolet Rays
Packaging:
BGA (Ball Grid Array): A type of surface-mount packaging where multiple solder balls are placed on the chip mounting substrate in a grid array pattern.
ASIC (Application Specific Integrated Circuit): ASIC is a type of specialized chip that is custom-designed for a specific application. It includes dedicated chips for audio, video processing, and currently, many specialized AI chips can be considered as ASICs.
Wirebonding: Wirebonding is the process of using metal wires (such as gold or aluminum) and applying heat or ultrasonic energy to establish solid connections for internal wiring within a solid-state circuit. It refers to the interconnection between the chip and the circuit or lead frame.
Die bonding: The process of connecting a chip to its package.
Flipchip: Inverted chip packaging involves depositing solder balls on I/O pads, then flipping the chip and heating it to bond the molten solder balls with the ceramic substrate.
COB (chip-on-board): Chip-on-board packaging involves attaching bare chips to a PCB using conductive or non-conductive adhesive, followed by wire bonding for electrical connections and encapsulating the chip and bonded wires with adhesive.
SOC (System On Chip): SOC is a term used for integrating various components such as CPU, bus, peripherals, etc., into a single chip. For example, a mobile processor is a complex SOC chip.
SIP (System In Package): SIP packaging involves integrating different functional bare chips, including CPU, GPU, memory, etc., within a single package, thereby creating a complete chip system.
SOP (Small Outline Package): A small form-factor IC package where leads are pulled out in two directions.
DAF (Die Attach Film): A bonding process using a thin film for die attachment.
CMOS (Complementary Metal Oxide Semiconductor): CMOS refers to a technology used in manufacturing integrated circuits or the chips produced using this technology. It's a type of RAM chip found on computer motherboards, used for storing data such as BIOS settings due to its read/write capability.
JEDEC (Joint Electron Device Engineering Council Standards): Standards governing package outlines and dimensions in the United States.
