Research on the problem of silicon substrate of nitride outer outer extension

release time:2022-03-17Author source:SlkorBrowse:2297

Abstract: With the continuous breakthrough of silicon-based gallium nitride epitaxial technology, the localization of its special silicon substrate materials has become increasingly prominent. This paper analyzes the problems of dense and split edge slip lines after domestic wafer epitaxy, and puts forward the parameters and technical indexes of silicon wafer edge control and mechanical strength control, which points out a certain direction for the development of high-quality silicon substrate to meet the demand of power device-level GaN epitaxy.

Gallium nitride has the characteristics of high saturation electron rate, breakdown voltage, high temperature resistance, etc. It can be used to make high-temperature, high-frequency and high-power electronic devices (FETs) operating in extremely harsh environments, and applied to wireless station, satellite communications and other fields [1-2]. Especially in recent ten years, the development of wide bandgap semiconductor materials and devices represented by GaN is very rapid, which has played a great role in promoting the development and application of information science and technology. Therefore, the preparation of GaN epitaxial materials and devices has become a hot research topic at present, and all domestic research institutions and universities focus on epitaxial technology research to improve device performance. As the most promising silicon-based gallium nitride epitaxial technology, a breakthrough has been made and applied to production. As a special material, the silicon substrate, especially the 15.24 cm silicon substrate material, now mostly depends on imports. Major domestic silicon wafer manufacturers mostly focus on the research of discrete device silicon wafers and silicon epitaxial substrates, and lack of understanding of the particularity of gallium nitride epitaxial technology, which leads to many problems such as serious surface slip line after epitaxy, cracking and amorphous surface during epitaxy. It is of great significance to carry out research on silicon substrates for GaN epitaxy and form uniform technical specifications and processing requirements for promoting the localization and industrialization of silicon-based GaN substrates.

China Electronics Research Institute 46 is committed to the research and development of special silicon substrates for silicon-based gallium nitride epitaxy, and has in-depth cooperation with well-known domestic gallium nitride device research and development enterprises such as Sanan Optoelectronics, Jingneng Optoelectronics, Suzhou Nengxun and Rainbow Blue Light. It has explored and developed the localization and batch production of special LED substrates and RF HEMT silicon substrates, and formed certain standards. In this paper, the problems existing in the epitaxial process of domestic silicon substrate of RF HEMT, such as dense edge slip lines and substrate breakage, are analyzed and studied. By analyzing the processing defects of silicon materials and comparing the performance parameters of domestic and foreign substrates, the development control parameters of gallium nitride silicon substrate have been established, and high-quality polishing wafers with the same level as foreign substrates have been developed, which points out a certain direction for realizing the localization of gallium nitride epitaxial silicon substrates for power devices.
1 Experiment 1.1 Substrate Sheet Specifications

Preparation method: CZ (Czochralski method);

Conductive type: P type;

Doping agent: boron doping;

Orientation: < 111 >;

Diameter: 150.0± 0.3 mm；

Thickness: 1 000± 15 μm；

Single-sided polishing, no cleaning.

1.2 experimental results Gallium nitride epitaxial growth was carried out in the same furnace with 15.24 cm silicon single wafer produced by 46 and 15.24 cm silicon single wafer imported from Japan. During the growth process, the curvature curve of silicon wafer was monitored, and the epitaxial results were compared and analyzed.
1.2.1 slip line problem
At the same time, domestic chips and imported chips are grown in the same furnace, and dense slip lines appear on the surface of domestic chips, and the length exceeds 5 mm, as shown in Figure 1. There are relatively few slip lines at the edge of the inlet, and the length is less than 3 mm.

Fig. 1 Microscopic photograph of edge slip line

1.2.2 the problem of splinters

At the same time, three domestic wafers and three imported wafers were used for epitaxial growth in the same furnace. During the cooling process, all three domestic wafers were split into two halves, and all three imported wafers were intact. The curve of curvature change in the growth process is shown in Figure 2.

T/s
Fig. 2 Variation diagram of epitaxial growth curvature

2 analysis and discussion The lattice mismatch between silicon and gallium nitride is 17%, which leads to a large number of dislocations during the growth of epitaxial thin films. The difference of thermal expansion coefficient between silicon and gallium nitride leads to a large thermal mismatch. When the epitaxial process drops from high temperature to low temperature, an elastic strain is produced, which leads to a large tensile stress. Among them, there is a tensile stress in gallium nitride epitaxial layer and a compressive stress in silicon substrate, which makes the bending degree of silicon substrate change. When the bending strength of silicon substrate is poor, the quality of epitaxial layer will not only deteriorate under the stress.From the point of view of epitaxial growth of gallium nitride on silicon, it mainly focuses on the edge slip line and the crack. The slip line is usually directly related to the chamfer edge quality of the silicon wafer, and the crack depends on the mechanical strength of the silicon wafer, which is closely related to the design and processing conditions of the silicon wafer.
2.1 slip line control Chamfering of silicon wafer refers to grinding the cut silicon wafer into a certain target diameter and shape, eliminating cutting stress and mechanical damage at the edge, and preventing edge collapse, cracking and lattice defects in the subsequent processing. At the same time, it can effectively reduce the generation of silicon wafer epitaxial slip line. By analyzing the area and density of slip lines, we found that the closer to the edge of the silicon wafer, the denser the slip lines, the rougher the epitaxial surface and the local damage, while there was no slip line at all 2 cm away from the edge. Therefore, we believe that the main reason for the slip line is that the mechanical damage of the edge of the silicon wafer has not been completely removed, and the edge chamfering quality needs to be further improved.In this experiment, the chamfering machine we used is W-GM-4200, and the R-type grinding wheel is 22° Symmetrical chamfering, the chamfer removal amount is 0.8 mm, in which the grinding wheel with particle size of 18.0 μm is roughly inverted once to remove 0.5 mm, and the grinding wheel with particle size of 11.0 μm is precisely inverted once to remove 0.2mm. The chamfer quality is shown in Figure 3. As can be seen from Figure 3, there is still a relatively microscopic damaged area on the chamfer edge, which becomes the concentrated area of dislocation and mechanical damage during high-temperature epitaxy, and the defects start to extend inward from the edge.

Fig. 3 Chamfer edge of grinding wheel with grain size of 11.0μ m.

In the processing of 20.32～30.48 cm silicon single crystal polishing wafer, in order to reduce the edge defects and improve the subsequent yield, edge polishing or precision chamfering with high-precision grinding wheel is often used. At present, due to the limitation of cost and processing equipment, the edge polishing of 15.24 cm silicon wafer has not been applied in practice, and the edge condition mainly depends on the performance of grinding wheel [4]. In order to reduce the edge slip line, we can learn from the chamfering method of 20.32 cm silicon wafer, and use sintered grinding wheel or even resin wheel with grain size of 6.5 μm or 5.0 μm to chamfer, which can greatly reduce the edge damage defect and make the chamfered edge reach the edge quality as shown in Figure 4. At the same time, the step-by-step chamfering is adopted to reduce the amount of ring removal, and the acid etching process is combined to meet the edge requirement of GaN epitaxy.
2.2 mechanical strength control

When CZ silicon wafer with thickness of 1 000μm is used for epitaxial growth of gallium nitride, it shows that the internal stress of the silicon wafer itself is large in the thermal process, and the mechanical strength can not meet the requirements. The stress of silicon wafer comes from the internal stress generated during the growth of single crystal and the stress introduced during processing. The mechanical strength of silicon wafer mainly depends on the internal defects of silicon single crystal and the mechanical damage caused by processing. In order to improve the mechanical strength of silicon wafer, we should start from three aspects: crystal performance of silicon single crystal, damage control during processing, surface quality and geometric parameters control.
2.2.1 quality control of silicon single crystal

The internal defects and oxygen content of silicon single crystal have an important influence on the mechanical properties of silicon wafers. In addition, the doping, thickness and crystal orientation of silicon wafers are also important parameters that affect the mechanical strength of silicon wafers. We analyzed and tested domestic silicon wafers and imported silicon wafers respectively, and the results are shown in Table 1. The test results show that both domestic silicon wafers and imported silicon wafers adopt 1 000 μm thick P<111 > heavily doped boron substrate, the < 111 > crystal orientation is mainly to match the hexagonal wurtzite structure of gallium nitride and reduce lattice mismatch, and the heavily doped boron is to improve the mechanical strength of silicon wafers. The doping concentration of imported silicon wafers is one order of magnitude higher than that of domestic silicon wafers, and the resistivity reaches 0.003 6 Ω· Cm, this is a significant difference. There is no difference in oxygen and carbon concentration between domestic silicon wafers and imported silicon wafers, both of which are normal oxygen and carbon content values. However, there are fewer domestic silicon wafers with bulk defects, which shows that there is no difficulty in the preparation of basic single crystals, and the main thing is to control the resistivity of silicon wafers to be consistent with that of imported wafers.

In addition, the stress of the silicon single crystal mainly comes from the growth stress and the stress generated during the cooling process after the growth of the single crystal. At present, the growth technology of the 15.24 cm silicon single crystal is relatively mature, and the key lies in controlling the appropriate growth rate and avoiding the formation of local stress and internal stress due to the rapid cooling of the crystal. Under the same process conditions, the greater the stress of silicon single crystal, the greater the warpage of the cut silicon wafer. The smaller the stress of single crystal silicon, the smaller the warpage of the cut silicon wafer. By monitoring the slice warpage under the same process conditions, the growth process of silicon single crystal is optimized. Generally, the warpage of high-quality single crystal after cutting is not more than 15 μm m.

Table 1 Comparison of crystal parameters between domestic silicon wafers and imported silicon wafe

2.2.2 Damage control during processing

The damage produced in the machining process is mainly the surface damage and edge damage produced in the cutting and grinding process, which are the main factors affecting the strength of silicon wafers. Sumino et al. have studied the tensile properties of dislocation-free silicon single crystal, and found that the surface damage has great influence on the mechanical strength of single crystal, and the yield stress of silicon single crystal with surface damage is obviously lower. Other studies on flexural strength also show that [5], the less the surface damage, the higher the flexural strength. Slicing is the first process that causes the surface damage of the silicon wafer, and it is also the most serious process. Therefore, optimizing the cutting process conditions is particularly important to reduce the surface damage. Optimizing the multi-wire cutting process, adjusting the mortar flow rate and cutting temperature, and minimizing the warpage and curvature of the cut silicon wafer can effectively improve the subsequent bending strength of the silicon wafer. The damage caused by grinding with alumina powder with a nominal particle size of 8 μm can be divided into two parts: 1) The severe damage area consisting of dislocations, cracks and broken grains is located in the range of about 10 μm from the surface of the silicon wafer; 2) The high stress area is located in the range of (10 ~ 25) μ m from the surface of the silicon wafer. Therefore, when we use alkali etching to remove 8 ~ 10μ m, only the broken layer on the surface is partially removed, and the mechanical strength of silicon wafer is only improved compared with that of grinding plate. Due to alkali corrosion, the back surface roughness of domestic chips is as high as 0.6 μm m. By comparing the test results of back surface roughness, the surface roughness of imported chips is only 0.2 μm, which is equivalent to 1/3 of that of domestic chips. Therefore, after grinding, acid etching process should be adopted to remove 25 ~ 30μ m on one side, which can effectively remove the damaged surface layer and improve the mechanical strength. In addition, if necessary, double-sided polishing sheets can be used to greatly improve the mechanical strength of silicon wafers.

2.2.3 control of surface quality and geometric parameters
The 15.24 cm silicon substrate for GaN epitaxy should have a high-quality clean-free surface, that is, the particle size level should be controlled within 20 particles larger than 0.2 μm, and the surface fog value of more than 97% area should be controlled at 0.004 2× 0-6, and the surface roughness is less than 0.2 nm. Both domestic silicon wafers and imported silicon wafers meet the above surface requirements, but there are some differences in geometric parameters. The specific results are shown in Figure 5 and Figure 6. From the test results, the warpage of domestic silicon wafers is 21 ~ 40μ m, and the warpage is 10.00 ~ 15.00μ m; The warpage of the imported sheet is 4 μm and the curvature is 0.16 μm, which indicates that the imported sheet is super flat. Under the same conditions, the bending strength value of the silicon wafer before and after heat treatment is large, that is, the bending strength value at room temperature [6] can reflect the bending ability of the silicon wafer in the high-temperature device process. The bending curve of domestic silicon wafer and imported silicon wafer in the epitaxial process well illustrates this problem. Therefore, it is an important means to improve the mechanical strength of silicon wafers and reduce the subsequent chips by controlling the warpage and warpage during the processing of silicon wafers.

Fig. 5 Test results of geometric parameters of domestic silicon wafers

Fig. 6 Test results of geometric parameters of imported silicon wafers

3 Improved control conditions

According to the above test and analysis, we have formulated the processing control standard of silicon substrate for gallium nitride. See Table 2. According to the requirements of control parameters, we adjusted the processing conditions, and the epitaxial quality of the 15.24 cm P heavily doped silicon single-sided polishing wafer was the same as that of foreign substrates.

4 Conclusion

In order to solve the problem of slip lines and cracks after silicon-based gallium nitride epitaxy for power devices, we must improve the edge quality and mechanical strength of silicon wafers. This requires us to organically combine the surface control technology of 15.24 cm silicon polishing wafer for silicon epitaxy, the geometric parameter control technology of MEMS silicon wafer and the edge control technology of 20.32～30.48 cm IC silicon wafer in the traditional industry to form a special technical standard for gallium nitride silicon substrate, so as to meet the development requirements of subsequent industrialization.

Table 2 Specification Requirements of Silicon Substrate for GaN Epitaxy

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